Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 79)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 79
B.10.6 DSP 25MHz Clock Synchronization
The PCIE-8120 card provides clock synchronization for the entire DSP array to ensure equal
processing time on computing tasks that are shared between two or more DSP units. The
synchronized main DSP operating clock is 25.00 MHz.
B.10.7 OPUS Debug Port
A debug port is available for low level debugging of individual DSP units via the vendor specific
Opus Studio development suite.
 Opus debug port via connector P5001
 16-Pin 1,27mm pitch micro header
 DSP debug port selection via CPLD.
DSPx_USER_HW_CONF[
14] CPLD 0 = Unique factory-burned per-chip MAC
address
1 = TFTP server with IP derived from
00:0C:90:02:xx
DSPx_USER_HW_CONF[
15] CPLD 0 = TFTP server at 192.168.1.200
1 = TFTP server with IP derived from
192.168.xx
BOOT_MODE[3:0] HW Strapping Strapped by resistor to
0100 = BOOTP on EMAC 2 on SERDES 2
Table B-6 DSP Control Signals (continued)
Signal Group Controlled by Description