Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 76)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 76
B.9.3 CPLD Upgrade
The CPLD offers a functionality to reprogram its configuration data under host software
control. The procedure is not FAIL-SAFE status. This means if a reprogramming procedure fails,
the whole card becomes unusable and needs to be reprogrammed via H/W (download cable).
B.10 DSP Array
The PCIE-8120 DSP Array can be populated with up to 12 instances of Octasic's DSP OCT2224M
System-On-Chip device, which is specialized for media gateway applications. For more
information on the Octasic DSP OCT2224M, refer to the OCT2200M Hardware Specification listed
in
Table "Related Specifications" on page 91 .
The following sections describe specific aspects of the PCIE-8120 design:
B.10.1 DSP Overview
The Octasic OCT2224M DSP is part of the OCT2200 series of devices which is a family of Digital
Signal Processors (DSP) based on the Opus 2 architecture developed by Octasic. It is targeting
voice and video applications for telephony infrastructure applications.
The OCT2224M is composed of five major subsystems:
 The Opus2 DSP subsystem
 The DDR Memory Subsystem
 The High-speed I/O Subsystem (Ethernet MAC Engines)
 The Resources Subsystem (GPIO)
 The Maintenance Subsystem (Boot Controller)
The main features of the OCT2224M are:
 24 Opus2 cores with 144k bytes of L1 memory per core
 C programmable DSP
 484-Pin BGA 1.0mm pitch
 4W typical power consumption
 Secure custom booting capability