Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 61)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 61
According to the PCI Express Card Electromechanical Specification Rev.2.0.2007.PCISIG CEM
2.04/11/2007, the PERST# signal indicates a system power good status combined with a card
reset function. Therefore, it cannot be used as a power good signal to the cards power-up
control for the local DC/DC units. To keep up with the timing requirements for the PERST#
signal, the local power control must enable the DC/DC units immediately after card edge
power appears. An undervoltage-lockout circuitry is used to provide a status signal that
indicates when the 12V main supply is within the allowed range:
 DC/DC enable for VP12 > 11.08V (calculated)
 DC/DC disable for VP12 < 8.5V (calculated)
B.5 Card Clock Architecture
The following figure provides an overview of the Card Clock Architecture of PCIE-8120:
Figure B-6 Card Clock Scheme
PCIe_
x4
25.000MHz
PCIe_ RefCLK
100MHz
25.000MHz
20MHz
PHY
88E1512
PHY
88E1111
PHY
88E1512
PHY
88E1111 25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
25.000MHz
LVC x12 buffer
12