Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 68)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 68
 Optional external Flash for persistent storage of user configuration data
– AT25256 device, 256kbits density, 8S1 SOIC package.
B.9.1 Card Power Management
The CPLD on the PCIE-8120 fulfills the functionality of a power management controller for the
card. The power-up and power-down control is based on the input signals.
 Internal power good status, that is, 3.3V from PCIE slot is present and the device has
started properly.
 VP12_FAIL signal indicating when the 12V main supply is not within the allowed range.
 PERST# signal from PCIE connector indicating the system preparing to go into operation
or leaving operational mode.
 VPx_PWRGD status signals of the on board DC/DC units.
Based on the status of the input signals, the following control signals display output:
 VPx_PWREN enables/disables the DC/DC units according to power-up/down timing
sequence requirements.
– Default power-up/down sequence is simultaneous.
 PWRDN_VP discharges the residual voltage levels after powering off the DC/DC units.
B.9.2 Interfaces and S/W control
B.9.2.1 MDIO
The MDIO[1] channel from the second SerDes port of the NIC is connected to the CPLD for
basic S/W access via mapped pseudo-PHY registers. A card specific enhanced network card
driver is necessary to make use of the functionality that is provided through the CPLD. For more
information on interfaces and S/W control, see
PCIE-8120 Software Package on page 32 .
B.9.2.2 Card Variant MOD_ID
The card provides a 4-bit wide H/W strapped ID (MOD_ID<3..0>). It is used to identify the
variant of the card. Based on the variant, some settings in the CPLD are different or specific
registers are not available.