Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 67)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 67
B.8 Media Flow Aggregator (MFA) Unit
The PCIE-8120 is optionally equipped with an Octasic OCT1503 MFA FPGA. The purpose of the
device is to aggregate an array of Ethernet devices (i.e., the OCT2224 DSP array) to form a
single logical node. For more information on Octasic OCT1503 MFA FPGA
, see OCT1503 MFA
FPGA Specifications. 2012. OCT1503DS9000 listed in Table "Related Specifications" on page 91 .
The MFA provides following features:
 FPGA design based on Altera EP3C25F256 device (Cyclone III Family).
 Field update programming through ethernet API.
 Interfaces: 2x GMII via MFA PHY 1&2 connected to VSW (default) or MSW based on
assembly option
– Interface MFA#1 used as device port (DSP side).
– Interface MFA#2 used as aggregated port (Network & control processor).
 Serial debug port option (RS232) via 3-Pin header P4201.
B.9 Glue Logic - CPLD
The PCIE-8120 card is equipped with a CPLD to support additional functionality that is required
by the design but not provided by the main components selected for the card. The functional
details are as follows:
 Lattice MachXO2-1200U, -4 device, 256-Ball caBGA.
 Single 3.3V supply from card edge connector.
 Internal 20MHz clock and power-up watchdog.
 Internal UFM stores H/W settings and product-specific information.