Artesyn PCIE-8120 Installation and Use (July 2014) - Manual (Page 69)

PCIE-8120 Hardware Description
PCIE-8120 Installation and Use (6806800R89C) 69
The OS device driver or user mode S/W can make use of the MOD_ID to make user specific
settings or specific functions available for the respective card.
B.9.2.3 Card BASE_ID
The Card provides a 4-bit address register for the DSP array (BASE_ID<3...0>). It is used to
differentiate multiple cards within a system from S/W point of view. It can be used to store the
IP address range of a card in the UFM or to reconfigure an exchanged card to respond to the
same IP address range than the original card.
The default value for BASE_ID<3..0> is 0b1111.
B.9.2.4 Opus Debug Port Multiplexer
The CPLD contains multiplex logic to select an individual DSP unit for debugging. The signals
from the OCT-SBDI2 Pod connection header are routed to the CPLD and the CPLD has a set of
SBDI output signals to every of the twelve DSP units. For more information on how to set up
OCT-SBDI2 debug connection, refer to OCT2200UG8002 user guide listed in
Table "Related
Specifications" on page 91 . Also, refer to OPUS Debug Port on page 79 .
B.9.2.5 SMBus and PVT_I2C Bus
The PCIE-8120 card provides connectivity to the PCI Express connector SMBus. Additionally, a
private I2C bus (PVT_I2C) is available that accesses the onboard sensor devices. Both are
connected to the CPLD to allow access to the sensor information via SMBus or through the Host
system via MDIO.
Table B-1 Card Variant MOD_ID
Order Number MOD_ID<3...0>
PCIE-8120-A12 0111
PCIE-8120-V12 0111
PCIE-8120-A04 0100
PCIE-8120-V04 0100
PCIE-8120-A12-N 1000
PCIE-8120-V12-N 1000