Development board block diagram, Handling the board – Altera Cyclone III LS FPGA Development Board User Manual
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1–4
Chapter 1: Overview
Development Board Block Diagram
Cyclone III LS FPGA Development Board Reference Manual
© October 2009 Altera Corporation
Development Board Block Diagram
shows the block diagram of the Cyclone III LS FPGA development board.
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c
Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Figure 1–1. Cyclone III LS FPGA Development Board Block Diagram
EP3CLS200F780
Port B
Port A
EEPROM
(32 Kbit I
2
C)
2x16 LCD
Push-button
Switches,
DIP Switches,
LEDs
CPLD
64 Mbyte
Flash
2 Mbyte
SSRAM
512 Mbyte
DDR2 (x16)
Gigabit
Ethernet
PHY (RGMII)
Clock_SMA
Programmable Oscillator
100 M, 125 M, 156.25 M,
SMA (LVPECL)
Embedded
Blaster
USB
2.0
x47
x16
x2 CLK IN
x2
x11
x13
x26 ADDR
Config I/O
x74
CLKIN x2
CLKOUT x2
x74
CLKIN x3
CLKOUT x3
JTAG Chain
x32 DATA
x1 CLK IN
(1.8 V)
Migratable to
EP3CLS70F780
Z
Z
66.6 MHz
512 Mbyte
DDR2 (x16)
x47
SMA
Anti-Tamper
Example
Design
x6
(LVPECL)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)