Altera Cyclone III LS FPGA Development Board - Manual (Page 22)

2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation
Figure 2–5 shows the PFL configuration.
Figure 2–5. PFL Configuration
MAX II CPLD EPM2210
System Controller
FPGA_DATA [0]
FPGA_DCLK
FLASH_A [25:1]
FLASH_D [15:0]
DATA [0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
2.5 V
10 k
nCE
CFI
Flash
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [25:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_RYBSYn
FLASH_RYBSYn
FPGA_nCONFIG
FPGA_CONF_DONE
FLASH_ADVn
FPGA_nSTATUS
2.5 V
10 k
FLASH_ADVn
CONF_DONE_LED
2.5 V
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RESETn
PS Port
Flash Interface
56.2
100 MHz
2.5 V
2.5 V
ERROR
FACTORY
LOAD
CLK_SEL
CLK_ENABLE
USER_PGM
USB_DISABLEn
JTAG_SECURE
AT_ACTIVE
MAX_DIP1
MAX_DIP0
MAX_RESETn
PGM_CONFIG
PGM_SEL
PGM_LED0
PGM_LED1
PGM_LED2
DIP Switch
USB BLASTER
2.5 V
56.2 100
50 MHz
FPGA_INIT_DONE
CONF_DONE
VCCA_SHDNn_PB
56.2
1 k
2x1
Header
2.5 V
10 k