Altera Double Data Rate I/O - Manual (Page 4)

Parameter Description
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).
Select Use ‘aset’ port for asynchronous preset (aset)
.
If you are not using any of the asynchronous clear
options, select Not used and specify whether
registers should power up high or low by turning
on/off Registers power up high.
Use ‘outclocken’ port Turn on this option to add a clock enable port to
control when data output is clocked in. This signal
prevents data from being passed through.
Invert ‘dataout’ output Turn on this option to invert the
dataout[]
output
port. This option is available for Cyclone III and
Cyclone II devices only.
Use output enable port Turn on this option to create an output enable input
port (
oe
) to control when the data is set out to the
dataout
port.
Use ‘oe_out’ port to connect to tri-state output
buffer(s)
Turn on this option to create an output enable port
for the bidirectional
padio
port. This port is
available for Stratix III and Cyclone III devices only.
Register ‘oe’ port Turn on this option tp register the output-enable
(
oe
) input port.
Delay switch-on by half a clock cycle Turn on this option to use an additional
oe
register.
When the additional
oe
register is used, the output
pin is held at high impedance for an extra half clock
cycle after the
oe
port goes high.
Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr).
Select Use ‘sset’ port for synchronous preset (sset).
If you are not using any of the synchronous clear
options, select Not used.
The synchronous reset option is available for
Arria GX, Stratix III, Stratix II, Stratix II GX,
Stratix, Stratix GX, HardCopy II, and HardCopy
Stratix devices only.
Table 3: ALTDDIO_BIDIR Parameter Settings
This table lists the parameter settings for the ALTDDIO_BIDIR IP core. The ALTDDIO_BIDIR IP core combines
the ALTDDIO_IN and ALTDDIO_OUT IP core functionality into a single IP core, which instantiates
bidirectional DDR ports.
Parameter Description
Currently selected device family Specify the Altera device family you are using.
4 ALTDDIO Parameter Settings
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2015.01.23
Altera Corporation Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
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