Ddr sdram, ddr2 sdram and rldram ii memory, Qdr sram and qdrii sram memory interfaces, High-speed interface applications – Altera Double Data Rate I/O User Manual
Page 2: Altddio resource utilization and performance
The DDR registers interface with DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDR SRAM, and QDRII
SRAM memory devices. You can also use the DDR I/O registers as a SERDES bypass mechanism in LVDS
applications. This section provides information about the following DDR I/O applications:
• DDR SDRAM, DDR2 SDRAM, and RLDRAM II memory interfaces
• QDR SRAM and QDRII SRAM memory interfaces
• High-speed interface applications
DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory
DDR SDRAM, DDR2 SDRAM, and RLDRAM II write and read data at twice the clock rate by capturing
data on both the positive and negative edge of a clock.
DDR and DDR2 SDRAM are JEDEC standards. RLDRAM II devices have minimal latency to support
designs that require fast response times. These DDR memory interfaces use a variety of I/O standards,
such as SSTL-II, 1.8-V HSTL, LVTTL, and LVCMOS.
Related Information
The DDR and DDRII SDRAM controller is available by downloading the Altera DDR SDRAM Controller
MegaCore function
QDR SRAM and QDRII SRAM Memory Interfaces
The QDR and QDRII SRAM standard is defined jointly by Cypress Semiconductor Corporation,
Integrated Device Technology, Inc., and Micron Technology, Inc.
QDR and QDRII SRAMs have separate DDR read and write ports that pass data concurrently. The
combination of concurrent transactions and DDR signaling allows data to be passed four times faster than
by conventional SRAMs. The I/O standards used for QDR SRAM devices are 1.5-V HSTL class I and II.
QDRII SRAMs use both 1.5-V and 1.8-V HSTL class I.
High-Speed Interface Applications
High-speed interface applications use various differential standards, such as LVDS, LVPECL, PCML, or
HyperTransport technology to transfer data.
These standards often use DDR data. Stratix series devices implement high-speed standards either by
using the dedicated differential I/O SERDES blocks or by bypassing SERDES and using the DDR I/O
circuitry in SERDES bypass mode. DDR IP cores, PLLs, and shift registers are all used in SERDES
functionality.
Related Information
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ALTDDIO Resource Utilization and Performance
For details about the resource utilization of the ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR
IP cores in various devices, and the performance of devices that include these IP cores, refer to the
Parameter Editor and the compilation reports for each device.
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DDR SDRAM, DDR2 SDRAM and RLDRAM II Memory
UG-DDRMGAFCTN
2015.01.23
Altera Corporation
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide