Altera Double Data Rate I/O - Manual (Page 3)

ALTDDIO Parameter Settings
These tables list the parameter settings for the ALTDDIO IP cores.
Table 1: ALTDDIO_IN Parameter Settings
This table lists the parameter settings for the ALTDDIO_IN IP core.
Parameter Description
Currently selected device family Specify the Altera ® device family you are using.
Width: (bits) Specify the width of the data buses.
Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).
Select Use ‘aset’ port for asynchronous preset (aset)
.
If you are not using any of the asynchronous clear
options, select Not used and specify whether
registers should power up high or low by turning
on/off Registers power up high.
Synchronous clear and synchronous set ports Select Use ‘sclr’ port for synchronous clear (sclr).
Select Use ‘sset’ port for synchronous preset (sset).
If you are not using any of the synchronous clear
options, select Not used.
The synchronous reset option is available for
Arria GX, Stratix III, Stratix II, Stratix II GX,
Stratix, Stratix GX, HardCopy II, and HardCopy
Stratix devices only.
Use ‘inclocken’ port Turn on this option to add a clock enable port that
controls when data input is clocked in. This signal
prevents data from being passed through.
Invert input clock When enabled, the first bit of data is captured on
the rising edge of the input clock. If not enabled, the
first bit of data is captured on the falling edge of the
input clock.
Table 2: ALTDDIO_OUT Parameter Settings
This table lists the parameter settings for the ALTDDIO_OUT IP core.
Parameter Description
Currently selected device family Specify the Altera device family you are using.
Width: (bits) Specify the width of the data buses.
UG-DDRMGAFCTN
2015.01.23
ALTDDIO Parameter Settings 3
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Altera Corporation
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