Altera Double Data Rate I/O - Manual (Page 12)

Design Example 2: 8-Bit DDR Divider Using ALTDDIO_BIDIR
This section presents a design example that uses the ALTDDIO_BIDIR IP core to generate a divider.
When you are finished with this example, you can incorporate it into your overall project.
In this example, you perform the following tasks:
• Create a divider using the ALTDDIO_BIDIR and lpm_divide megafunctions and the MegaWizard
Plug-in Manager
• Implement the design and assign the Stratix EP1S10F780C6 device to the project
• Compile and simulate the design
Generate a Divider Using ALTDDIO_BIDIR
The new megafunction created in this example is added to the top-level file in your Quartus II project.
Create the ALTDDIO_BIDIR Module
Follow these steps to create the
ALTDDIO_BIDIR
module:
1. Unzip the ALTDDIO_DesignExample_ex2.zip file to any working directory on your PC.
2. In the Quartus II software, open the ex2.qar project .
3. On the Tools menu, select MegaWizard Plug-In Manager.
4. In the MegaWizard Plug-In manager dialog box, select Create a new custom megafunction variation,
and click Next. The MegaWizard Plug-In Manager page displays.
5. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in this
table. Click Next to advance from one page to the next.
Parameter
Editor Page
Parameter Value
2a
Which megafunction would you like to customize In the I/O folder, select
ALTDDIO_BIDIR
Which device family will you be using? Stratix
Which type of output file do you want to create? VHDL
What name do you want for the output file? alt_bid
Return to this page for another create operation Turned off
12 Design Example 2: 8-Bit DDR Divider Using ALTDDIO_BIDIR
UG-DDRMGAFCTN
2015.01.23
Altera Corporation Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
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