Altera MAX 10 Embedded Multipliers User Manual
Page 29
GUI Parameter
Parameter
Condition
Value
Description
Pipeline Register >
What is the source for
asynchronous clear
input?
ADDNSUB_
MULTIPLIER_
PIPELINE_
ACLR[1]
Adder Operation
> More Options
• Aclr0–Aclr2
• None
Specifies the source for
asynchronous clear
input.
What operation should
be performed on
outputs of the second
pair of multipliers?
MUTIPLIER3_
DIRECTION
General > What
is the number of
multipliers? = 4
—
Specifies whether the
fourth and all
subsequent odd-
numbered multipliers
add or subtract their
results from the total.
Values are add and
subtract. If Variable is
selected, the
addnsub3
port is used.
‘
addnsub3
’ input
controls the sign (1
add/0 sub) - More
Options
—
—
—
High ‘
addnsub3
’ input
indicates add and low
‘
addnsub3
’ input
indicates subtract.
Register ‘
addnsub3
’
input
—
—
On or Off
Turn on this option if
you want to enable the
register of ‘
addnsub3
’
input.
Add an extra pipeline
register
—
—
On or Off
Turn on this option if
you want to enable the
extra pipeline register.
Input Register > What
is the source for clock
input?
ADDNSUB_
MULTIPLIER_
REGISTER[3]
Adder Operation
> More Options
Clock0–Clock3
Specifies the source for
clock input.
Input Register > What
is the source for
asynchronous clear
input?
ADDSUB_
MULTIPLIER_
ACLR[3]
Adder Operation
> More Options
• Aclr0–Aclr2
• None
Specifies the source for
asynchronous clear
input.
Pipeline Register >
What is the source for
clock input?
ADDNSUB_
MULTIPLIER_
PIPELINE_
REGISTER[3]
Adder Operation
> More Options
Clock0–Clock3
Specifies the source for
clock input.
Pipeline Register >
What is the source for
asynchronous clear
input?
ADDNSUB_
MULTIPLIER_
PIPELINE_
ACLR[3]
Adder Operation
> More Options
• Aclr0–Aclr2
• None
Specifies the source for
asynchronous clear
input.
UG-M10DSP
2014.09.22
ALTMULT_ADD Parameter Settings
6-5
ALTMULT_ADD (Multiply-Adder) IP Core References
Altera Corporation