Altera MAX 10 Embedded Multipliers - Manual (Page 18)

GUI Parameter Parameter Condition Value Description
Input Register > What
is the source for clock
input?
SIGN_REG_B Input
Representation >
More Options
Clock0–Clock3 Specifies the source for
clock input.
Input Register > What
is the source for
asynchronous clear
input?
SIGN_ACLR_B Input
Representation >
More Options
• Aclr0–Aclr2
• None
Specifies the source for
asynchronous clear
input.
Pipeline Register >
What is the source for
clock input?
SIGN_
PIPELINE_
REG_B
Input
Representation >
More Options
Clock0–Clock3 Specifies the source for
clock input.
Pipeline Register >
What is the source for
asynchronous clear
input?
SIGN_
PIPELINE_
ACLR_B
Input
Representation >
More Options
• Aclr0–Aclr2
• None
Specifies the source for
asynchronous clear
input.
Table 5-2: ALTMULT_ACCUM Parameters - Extra Modes
GUI Parameter Parameter Condition Value Description
Create a shiftout
output from A input of
the last multiplier
— — On or Off Turn on this option to
create a shiftout output
from A input of the last
multiplier.
Create a shiftout
output from B input of
the last multiplier
— — On or Off Turn on this option to
create a shiftout output
from B input of the last
multiplier.
Add extra register(s) at
the output
— — On By default, output
register must be
enabled for
accumulator.
What is the source for
clock input?
OUTPUT_REG Outputs
Configuration >
More Options
Clock0–Clock3 Specifies the clock
signal for the registers
on the outputs.
What is the source for
asynchronous clear
input?
OUTPUT_ACLR Outputs
Configuration >
More Options
• Aclr0–Aclr2
• None
Specifies the asynchro‐
nous clear signal for
the registers on the
outputs.
Add [] extra latency to
the output
— Outputs
Configuration >
More Options
0, 1, 2, 3, 4, 5, 6,
7, 8, or 12
Specifies the extra
latency to add to the
output.
UG-M10DSP
2014.09.22
ALTMULT_ACCUM Parameter Settings 5-3
ALTMULT_ACCUM (Multiply-Accumulate) IP Core References Altera Corporation
Send Feedback