Altera MAX 10 Embedded Multipliers - Manual (Page 23)

ALTMULT_ACCUM Ports
Table 5-5: ALTMULT_ACCUM IP Core Input Ports
Port Name Required Description
accum_sload
No
Causes the value on the accumulator feedback path to go to
zero (0) or to
accum_sload_upper_data
when concatenated
with 0. If the accumulator is adding and the
accum_sload
port
is high, then the multiplier output is loaded into the
accumulator. If the accumulator is subtracting, then the
opposite (negative value) of the multiplier output is loaded
into the accumulator.
aclr0
No The first asynchronous clear input. The
aclr0
port is active
high.
aclr1
No The second asynchronous clear input. The
aclr1
port is
active high.
aclr2
No The third asynchronous clear input. The
aclr2
port is active
high.
aclr3
No The fourth asynchronous clear input. The
aclr3
port is active
high.
addnsub
No Controls the functionality of the adder. If the
addnsub
port is
high, the adder performs an add function; if the
addnsub
port
is low, the adder performs a subtract function.
clock0
No Specifies the first clock input, usable by any register in the IP
core.
clock1
No Specifies the second clock input, usable by any register in the
IP core.
clock2
No Specifies the third clock input, usable by any register in the IP
core.
clock3
No Specifies the fourth clock input, usable by any register in the
IP core.
dataa[]
Yes Data input to the multiplier. The size of the input port
depends on the
WIDTH_A
parameter value.
datab[]
Yes Data input to the multiplier. The size of the input port
depends on the
WIDTH_B
parameter value.
ena0
No Clock enable for the
clock0
port.
ena1
No Clock enable for the
clock1
port.
ena2
No Clock enable for the
clock2
port.
ena3
No Clock enable for the
clock3
port.
5-8 ALTMULT_ACCUM Ports
UG-M10DSP
2014.09.22
Altera Corporation ALTMULT_ACCUM (Multiply-Accumulate) IP Core References
Send Feedback