Rockwell Automation 1771-VHSC , D17716.5.74 Very High S - Manual (Page 74)

Period/Rate and Continuous/Rate Examples E–3
The following examples demonstrate the operation of the outputs in
period/rate mode of operation for the 1771-VHSC revision B
modules.
1. If scaler = 1
The 4MHz count, frequency, new data bit, totalized count and
outputs will be updated on the trailing edge of every pulse at the
gate/reset input.
2. If scaler
0 1 and (Number of pulses occurring in 250ms) <
(1/2 scaler + 1)
The 4MHz count will remain at 999,999, the frequency will
remain at 0. The outputs will be on if A (output on preset) > B
(output off preset). The outputs will be off if A (output on preset)
< B (output off preset).
3. If scaler
0 1 and (1/2 scaler + 1) < (Number of pulses occurring
in 250ms) < (1.5 scaler)
The outputs, 4MHz count, frequency, and new data bit will be
updated on the leading (not inverted) edge of the scaler + 1
number pulse occurring in 250ms.
Note: Any previous pulses less than the scaler number that
occurred at any time will effect the module update. For example,
with a scaler of 4, and applying six pulses every 300ms at the
gate/reset terminal, the module will do an update every other
burst of six pulses because there are “left over” pulses from the
previous burst.
4. If scaler
0 1 and (Number of pulses occurring in 250ms) > 1.5
scaler
The outputs, 4MHz count, frequency and new data bit will be
updated on the leading edge (not inverted) of the scaler + 1
number pulse.
In all cases, if the incoming pulses stop the 4MHz count will go
to 999,999, the frequency will go to 0, the new data bit will be
set, and the outputs will be updated accordingly 250–260ms after
the last pulse.
If the pulses have stopped for more than 250ms the first time that
the output should be updated, it will occur within 1.5ms (3ms in
BCD) of the actual pulse.
The totalized count is updated every scaler number of pulses, but
due to “left over” pulses may increment by more than the total
number of pulses that occurred. For example, with a scaler of 2
and the gate/reset terminal receiving 3 pulses every 300ms, the
total count will increment by 4 every fourth burst of pulses.
Operation of Outputs in
Period/rate Mode
(1771ĆVHSC Revision B
Modules)