Analog, 1 analog timing, 2 vref – Cirrus Logic CS4955 User Manual
Page 32: 3 iset, 4 dacs, 1 luminance dac, Analog timing, Vref, Iset, Dacs

CS4954 CS4955
32
DS278F6
7.
ANALOG
7.1
Analog Timing
All CS4954/5 analog timing and sequencing is de-
rived from the 27 MHz clock input. The analog out-
puts are controlled internally by the video timing
generator in conjunction with master and slave tim-
ing.
Since the CS4954/5 is almost entirely a digital cir-
cuit, great care has been taken to guarantee analog
timing and slew rate performance as specified in
the NTSC and PAL analog specifications. Refer-
ence the Analog Parameters section of this data
sheet for the performance specifications.
7.2
VREF
The CS4954/5 can operate with or without the aid
of an external voltage reference. The CS4954/5 is
designed with an internal voltage reference genera-
tor that provides a VREFOUT signal at the VREF
pin. The internal voltage reference is utilized by not
making a connection to the VREF pin. The VREF
pin can also be connected to an external precision
1.232 volt reference, which then overrides the in-
ternal reference.
7.3
ISET
All six of the CS4954/5 digital to analog converter
DACs are output current normalized with a com-
mon ISET device pin. The DAC output current per
bit is determined by the size of the resistor connect-
ed between ISET and electrical ground. Typically a
4 K
Ω, 1% metal film resistor should be used. The
ISET resistance can be changed by the user to ac-
commodate varying video output attenuation via
post filters and also to suit individual preferred per-
formance needs.
In conjunction with the ISET value, the user can
also independently vary the chroma, luma and col-
orburst amplitude levels via host addressable con-
trol register bits that are used to control internal
digital amplifiers. The DAC output levels are de-
fined by the following equations:
VREF/RISET = IREF
(e.g., 1.232 V/4K
Ω = 308 μA)
CVBS/Y/C/R/G/B outputs in low impedance mode:
VOUT (max) = IREF*(16/145)*1023*37.5
Ω = 1.304V
CVBS/Y/C/R/G/B outputs in high impedance mode:
VOUT (max) = IREF*(4/145)*1023*150
Ω = 1.304 V
7.4
DACs
The CS4954/5 is has six independent, video-grade,
current-output, digital-to-analog converters
(DACs). They are 10-bit DACs operating at a
27 MHz two-times-oversampling rate. All six
DACs are disabled and default to low power mode
upon RESET. Each DAC can be individually pow-
ered down and disabled. The output-current-per-bit
of all six DACs is determined by the size of the re-
sistor connected between the ISET pin and ground.
7.4.1 Luminance DAC
The Y output pin is driven from a 10-bit 27 MHz
current output DAC that internally receives the Y,
or luminance (black and white only) or CVBS data
based on its configuration. See
signed to drive proper video levels into a 37.5
Ω
load. Reference the detailed electrical section of
this data sheet for the exact Y digital to analog AC
and DC performance data. A EN_L enable control
bit in the Control Register 5 (0×05) is provided to
enable or disable the luminance DAC. To com-
pletely disable or for low power device operation,
the luminance DAC can be totally shut down via
the SVIDLUM_PD control bit in Control Register
4 (0×04). In this mode, turn-on using the control
register will not be instantaneous.