Cirrus Logic CS1631 - Manual (Page 34)

CS1630/31
34 DS954F3
6.12 Configuration 7 (Config7) – Address 39
6.13 Configuration 8 (Config8) – Address 40
7 6 5 4 3 2 1 0
PROBE PRCNT3 PRCNT2 PRCNT1 PRCNT0 - - -
Number Name Description
[7] PROBE
Configures the automated T
RES
probe operation that measures the resonant
frequency on the drain of the second stage FET using the reflected voltage
applied to the FBAUX pin for improved valley switching performance.
0 = Disables T
RES
probe
1 = Enables T
RES
probe
[6:3] PRCNT[3:0]
When PROBE=‘1’, sets the number of switching cycles TT
Cycles
between T
RES
probe measurements.
When PROBE=‘0’, sets the time for a quarter period of the resonant period
T
RES
.
[2:0] - Reserved
7 6 5 4 3 2 1 0
RSHIFT3 RSHIFT2 RSHIFT1 RSHIFT0 CH1_ZCD2 CH1_ZCD1 CH1_ZCD0 CH1CURMSB
Number Name Description
[7:4] RSHIFT[3:0]
Sets the number of right shifts performed on the second stage PID integrator
value to generate a 10-bit threshold value for the peak control comparator. For
peak rectify mode, the threshold is calculated by a right shift of the integrator
value. If RSHIFT[3:0] is set to 12, the 24-bit integrator is shifted right 12 times
and the remaining bits represent the threshold value provided to the peak con-
trol comparator.
[3:1] CH1_ZCD[2:0]
Sets fixed time delay T
CH1ZCD(Delay)
to account for the delay of the second
stage zero-current detection (ZCD) comparator during channel 1 switching
cycles when the voltage applied to the FBAUX pin falls below the 250mV ZCD
comparator threshold. Configuring T
CH1ZCD(Delay)
is essential for good quasi-
resonant (valley switching) performance. The value is an unsigned integer in
the range of 0
value7. The delay is defined by:
[0] CH1CURMSB
Most significant bit for the CH1CUR register (see "Channel 1 Output Current
(CH1CUR) – Address 41" on page 35).
TT
Cycles
16 P  RCNT[3:0]   15 + =
T
RES
4
-------------- 2 PRCNT[3:0] 50ns   =
T
CH1ZCD Delay  
CH1_ZCD = [2:0] 50ns 