2 post failure – Cirrus Logic CobraNet User Manual
Page 125
CobraNet Programmer’s Reference
Error Reporting
DS651PM25
©
Copyright 2006 Cirrus Logic, Inc.
125
8.2.2 POST Failure
Power on self-tests are performed during the boot process. If one of these tests fails, an
error code is displayed as a flashing pattern on the Fault indicator. Once the code has
been displayed, the interface will automatically attempt to reset itself. Typically the same
test will fail again resulting in repeated display of the failing error code.
Table 16. POST Failure Error Codes
Number of Fault
Indicator Flashes
Failed Test
1
Runtime code checksum error
2
Boot code checksum error
3
Xilinx configuration load failure
4
Error in MAC register access
5
Data error in PHY register access
6
Timeout error in PHY register access
8
SRAM error: bank 0 LS byte
9
SRAM error: bank 0 middle byte
10
SRAM error: bank 0 MS byte
11
SRAM error: bank 1 LS byte
12
SRAM error: bank 1 middle byte
13
SRAM error: bank 1 MS byte
14
Address or data bus data dependent failure
15
Ethernet loopback test failure
19
Unexpected interrupt occurred
20
Unexpected Xilinx configuration identification
21
Unexpected Xilinx configuration version
22
Sample clock range test failure
23
Sample clock not running