Adsp-ts201s – Analog Devices TigerSHARC ADSP-TS201S User Manual
Page 29
ADSP-TS201S
Rev. C
|
Page 29 of 48
|
December 2006
DS2–0
8
Static Pins—Must Be Constant
—
—
—
—
—
—
—
SCLKRAT2–0
8
Static Pins—Must Be Constant
—
—
—
—
—
—
—
ENEDREG
Static Pins—Must Be Connected to V
SS
—
—
—
—
—
—
—
STRAP SYS
9,
10
Strap Pins
1.5
0.5
—
—
—
—
SCLK
JTAG SYS
11,
12
JTAG System Pins
+2.5
+10.0
+12.0
–1.0
—
—
TCK
1
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2
For input specifications on FLAG3–0 pins, see
3
These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4
For additional requirement details, see
.
5
RST_IN clock reference is the falling edge of SCLK.
6
TDO output clock reference is the falling edge of TCK.
7
Reference clock depends on function.
8
These pins may change only during reset; recommend connecting it to V
DD_IO
/V
SS
.
9
STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.
10
Specifications applicable during reset only.
11
JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,
IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0,
L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP,
L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0,
L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO,
L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0,
SCLKRAT2–0, DS2–0, ENEDREG.
12
JTAG system output timing clock reference is the falling edge of TCK.
Figure 15. General AC Parameters Timing
Table 29. AC Signal Specifications (Continued)
(All values in this table are in nanoseconds.)
Name
Description
In
put S
e
tu
p
(M
in
)
In
put Hold
(M
in
)
Ou
tp
u
t V
a
li
d
(M
a
x
)
Ou
tp
u
t H
o
ld
(M
in
)
Ou
tp
u
t En
ab
le
(M
in
)
1
Ou
tpu
t Di
sab
le
(M
a
x
)
1
Re
fe
re
nce
Cl
ock
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
OUTPUT
VALID
OUTPUT
HOLD
OUTPUT
ENABLE
OUTPUT
DISABLE
INPUT
HOLD
INPUT
SETUP
1.25V
1.25V
1.25V
t
SCLK
OR
t
TCK