Rainbow Electronics AT90C8534 - Manual (Page 34)

AT90C8534
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ADC Multiplexer Select Register – ADMUX
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
•
Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0
The value of these three bits selects which analog input 5 - 0 is connected to the ADC. Selections 110 and 111 are
reserved and should not be used.
ADC Control and Status Register – ADCSR
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while
a conversion is in progress will terminate this conversion.
•
Bit 6 – ADSC: ADC Start Conversion
In Single Conversion Mode, a logical “1” must be written to this bit to start each conversion. In Free Run Mode, a logical “1”
must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been
enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated con-
version. This dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the actual conversion is finished, but before the result is
written to the ADC Data Registers. This allows a new conversion to be initiated before the current conversion is complete.
The new conversion will then start immediately after the current conversion completes. When a dummy conversion
precedes a real conversion, ADSC will stay high until the real conversion is finished.
Writing a 0 to this bit has no effect.
•
Bit 5 – ADFR: ADC Free Run Select
When this bit is set (one), the ADC operates in Free Run Mode. In this mode, the ADC samples and updates the data
registers continuously. Clearing this bit (zero) will terminate Free Run Mode.
•
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing
Bit 7 6 5 4 3 2 1 0
$07 ($27) – – – – – MUX2 MUX1 MUX0 ADMUX
Read/Write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 7. ADC Channel Selections
MUX2 MUX1 MUX0 Channel
0 0 0 ADIN0
0 0 1 ADIN1
0 1 0 ADIN2
0 1 1 ADIN3
1 0 0 ADIN4
1 0 1 ADIN5
1 1 0 reserved
1 1 1 reserved
Bit 7 6 5 4 3 2 1 0
$06 ($26) ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0