Rainbow Electronics AT90C8534 - Manual (Page 15)

AT90C8534
15
Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed and the result is stored back to the destination register.
Figure 21. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 22. On-Chip Data SRAM Access Cycles
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read
Wr
ite