Rainbow Electronics AT90C8534 - Manual (Page 23)

AT90C8534
23
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 – Res: Reserved Bit
This bit is reserved bits in the AT90C8534 and always reads as zero.
•
Bit 6 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode, unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit
just before the execution of the SLEEP instruction.
•
Bit 5 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power-down Mode is selected as Sleep Mode. For details, refer to the section “Sleep Modes”.
•
Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
•
Bit 2 – ISC1: Interrupt Sense Control 1
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK are set. If ISC1 is cleared (zero) a falling edge on INT1 activates the interrupt. If ISC1 is set (one), a rising edge on
INT1 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT1 wider than 40 ns will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
When changing the ISC1 bit, an interrupt can occur. Therefore, it is recommended to first disable INT1 by clearing its inter-
rupt Enable bit in the GIMSK register. Then ISC1 bit can be changed. Finally, the INT1 interrupt flag should be cleared by
writing a logical “1” to its interrupt Flag bit in the GIFR register before the interrupt is re-enabled.
•
Bit 1 – Res: Reserved Bit
This bit is reserved bits in the AT90C8534 and always reads as zero.
•
Bit 0 – ISC0: Interrupt Sense Control 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK are set. If ISC0 is cleared (zero), a falling edge on INT0 activates the interrupt. If ISC0 is set (one), a rising edge on
INT0 activates the interrupt. Pulses on INT0 wider than 40 ns will generate an interrupt. Shorter pulses are not guaranteed
to generate an interrupt.
When changing the ISC0 bit, an interrupt can occur. Therefore, it is recommended to first disable INT0 by clearing its inter-
rupt Enable bit in the GIMSK register. Then ISC0 bit can be changed. Finally, the INT0 interrupt flag should be cleared by
writing a logical “1” to its interrupt Flag bit in the GIFR register before the interrupt is re-enabled.
Sleep Modes
To enter any of the two sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed.
The SM bit in the MCUCR register selects which sleep mode, Idle or Power-down, is activated by the SLEEP instruction.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for four cycles,
executes the interrupt routine and resumes execution from the instruction following SLEEP. The contents of the register
file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the
Reset vector.
Idle Mode
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode, stopping the CPU but allowing
Timer/Counters, ADC and the interrupt system to continue operating. This enables the MCU to wake up from external
triggered interrupts as well as internal ones like the Timer Overflow and ADC interrupts.
Bit 7 6 5 4 3 2 1 0
$35 ($55) – SE SM – – ISC1 – ISC0 MCUCR
Read/Write R R/W R/W R R R/W R R/W
Initial value 0 0 0 0 0 0 0 0