Rainbow Electronics AT90C8534 - Manual (Page 22)

AT90C8534
22
Timer/Counter Interrupt Mask Register – TIMSK
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
•
Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $003) is executed if an overflow in Timer/Counter1 occurs, i.e., when the
Overflow Flag (Timer/Counter1) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
•
Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90C8534 and always reads as zero.
•
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
Timer/Counter Interrupt Flag Register – TIFR
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
•
Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared when fetching the interrupt vector.
Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1 (Timer/Counter1
Overflow Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed.
•
Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90C8534 and always reads as zero.
•
Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared when fetching the interrupt vector.
Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Over-
flow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. The external interrupts can be triggered by a falling or
rising edge.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after
the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this
4-clock-cycle period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is decremented by 2.
The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs
during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four
clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer is incremented by 2 and the
I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Bit 7 6 5 4 3 2 1 0
$39 ($59) – – – – – TOIE1 – TOIE0 TIMSK
Read/Write R R R R R R/W R R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$38 ($58) – – – – – TOV1 – TOV0 TIFR
Read/Write R R R R R R/W R R/W
Initial value 0 0 0 0 0 0 0 0