General interrupt mask register – gimsk, General interrupt flag register – gifr, General interrupt pin register – gipr – Rainbow Electronics AT90C8534 User Manual
Page 21: 21 general interrupt mask register – gimsk
AT90C8534
21
General Interrupt Mask Register – GIMSK
•
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The external interrupt is activated on falling or rising edge of the INT1 pin. The corresponding interrupt of External Interrupt
Request 1 is executed from program memory address $002. See also “External Interrupts”.
•
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The external interrupt is activated on falling or rising edge of the INT0 pin. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External Interrupts”.
•
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
General Interrupt Flag Register – GIFR
•
Bit 7 – INTF1: External Interrupt Flag 1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when fetching the
interrupt vector. Alternatively, the flag can be cleared by writing a logical “1” to it.
•
Bit 6 – INTF0: External Interrupt Flag 0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when fetching the
interrupt vector. Alternatively, the flag can be cleared by writing a logical “1” to it.
•
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
General Interrupt Pin Register – GIPR
•
Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
•
Bit 3 – IPIN1: External Interrupt Pin 1
Reading this bit returns the logical value present on input pin INT1 (after synchronization latches).
•
Bit 2 – IPIN0: External Interrupt Pin 0
Reading this bit returns the logical value present on input pin INT0 (after synchronization latches).
•
Bits 1..0 – Res: Reserved Bits
These bits are reserved bits in the AT90C8534 and always read as zero.
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
–
–
–
–
–
–
GIMSK
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
–
–
–
–
–
–
GIFR
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$10 ($30)
–
–
–
–
IPIN1
IPIN0
–
–
GIPR
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
x
x
0
0