Rainbow Electronics TS81102G0 - Manual (Page 17)

17
TS81102G0
2105C–BDC–11/03
Timing Diagrams with
Asynchronous Reset With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because
of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins
to obtain good setup and hold times between Clkln and the data.
Figure 12. Start with Asynchronous Rest, 1:8 Ratio, DR Mode
With a nominal tuning of DMUXDelAdj at 2 GHz, d1 and d2 data is lost because of the internal
clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain
good setup and hold times between Clkln and the input data. This timing diagram does not
change with the opposite phase of Clkln.
Figure 13. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode
TRAR
PWAR
TFAR
Clkn
ASyncReset
Internal Port Selection
(not available out of the DEMUX)
A B C D
d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
d10
d11
d12
d13
d14
d15
d16
d17
d3
d4
d5
d6
d7
d8
d9
d12 d13 d14 d15 d16 d17
E F G H B A C D E F G H
TPD
TCPD
TOD
TRDR TFDR
TROD/TFOD
TOD
TDRF TDRR TARDR
I[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
E[0..9]
F[0..9]
G[0..9]
H[0..9]
DR
TRAR
PWAR
TFAR
Clkn
ASyncReset
Internal Port Selection
(not available out of the DEMUX)
A B C D
d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
d10
d11
d12
d13
d14
d15
d16
d17
d3
d4
d5
d6
d7
d8
d9
d12 d13 d14 d15 d16 d17
E F G H B A C D E F G H
TPD
TCPD
TOD
TRDR TFDR
TROD/TFOD
TOD
TDRF TDRR TARDR
I[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
E[0..9]
F[0..9]
G[0..9]
H[0..9]
DR
TCPD