Table 48. overvoltage status register format – Rainbow Electronics MAX5961 User Manual
Page 37
MAX5961
0 to 16V, Quad, Hot-Swap Controller
with 10-Bit Current and Voltage Monitor
______________________________________________________________________________________
37
These fault register bits latch upon a fault condition, and
must be reset manually by writing a zero to the register,
or by restarting the affected channel as described in the
Autoretry or Latched-Off Fault Management
section.
FAULT_ Outputs
When an overcurrent event (fast-trip or slow-trip) causes
the MAX5961 to shut down the affected channel(s), a cor-
responding open-drain FAULT_ output is asserted low.
Note that the FAULT_ outputs are not asserted for shut-
downs caused by critical undervoltage or overvoltage.
The FAULT_ output is cleared when the channel is dis-
abled by pulling ON_ low or by clearing the Chx_EN1
or Chx_EN2 bits in register chxen.
ALERT Output
The ALERT output is an open-drain output that is assert-
ed low any time that a fault or other condition requiring
attention has occurred. The state of the ALERT output is
also indicated by bit 4 of the status3 register.
ALERT is the NOR of registers 0x5F, 0x63, 0x64, and 0x65,
so when the ALERT output goes low, the system microcon-
troller (µC) should query these registers through the I
2
C
interface to determine the cause of the ALERT assertion.
Table 48. Overvoltage Status Register Format
Description:
Overvoltage digital-compare status register (warning [3:0] and critical [7:4] overvoltage event
detection status)
Register Title:
fault1
Register Address:
0x64
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
RESET
VALUE
ch4_ov2
ch3_ov2
ch2_ov2
ch1_ov2
ch4_ov1
ch3_ov1
ch2_ov1
ch1_ov1
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Table 49. Overcurrent Warning Status Register Format
Description:
Overcurrent digital-compare status register (overcurrent warning event detection status)
Register Title:
fault2
Register Address:
0x65
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
RESET
VALUE
ch4_oi
ch3_oi
ch2_oi
ch1_oi
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Table 50. Circuit-Breaker Event Logging Register Format
Description:
Circuit-breaker slow- and fast-trip event logging
Register Title:
status0
Register Address:
0x5F
R
R
R
R
R
R
R
R
RESET
VALUE
ch4_st
ch3_st
ch2_st
ch1_st
ch4_ft
ch3_ft
ch2_ft
ch1_ft
--
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0