National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
Page 210
Index
Lab-PC+ User Manual
Index-14
© National Instruments Corporation
grounded signal sources (NRSE
configuration), 3-11 to 3-12
software programming choices
LabVIEW and LabWindows/CVI
software, 1-2
NI-DAQ driver software, 1-2 to 1-3
register-level programming, 1-3
specifications
analog input, A-1 to A-2
amplifier characteristics, A-2
dynamic characteristics, A-2
explanation, A-3
input characteristics, A-1
stability, A-2
transfer characteristics, A-1
analog output, A-4 to A-5
dynamic characteristics, A-4
explanation, A-4 to A-5
output characteristics, A-4
stability, A-4
transfer characteristics, A-4
voltage output, A-4
bus interface, A-6
digital I/O, A-5
environment, A-6
physical, A-6
power requirements, A-6
timing I/O, A-5 to A-6
triggers, A-6
Start Convert Register, D-19
Status Register
analog input circuitry programming, E-3
controlled data acquisition
programming, E-8
posttrigger mode, E-13
pretrigger mode, E-16
description, D-7 to D-8
freerun data acquisition programming, E-10
STB* signal
description, 3-16
Mode 1 input timing, 3-18
Mode 2 bidirectional timing, 3-20
Port C signal assignments (table), 3-16
switch settings. See jumper and switch
settings.
SWTRIG bit
controlled acquisition mode, E-7
posttrigger mode, E-12
pretrigger mode, E-16
description, D-10
freerun acquisition mode, E-10
multiple A/D conversions using EXTTRIG
signal, E-11
system noise, A-3
T
TBSEL bit
controlled acquisition mode, E-6
description, D-9
TCINTEN bit, D-11
technical support, F-1
theory of operation
analog input circuitry, 4-5
block diagram, 4-4
analog output circuitry, 4-9 to 4-10
block diagram, 4-9
block diagram, 4-1
data acquisition timing circuitry, 4-5 to 4-8
block diagram, 4-4
data acquisition rates, 4-7 to 4-8
multiple-channel (scanned) data
acquisition, 4-6 to 4-7
single-channel data acquisition, 4-6
digital I/O circuitry, 4-10 to 4-11
block diagram, 4-10
functional overview, 4-1 to 4-2
PC I/O channel interface circuitry, 4-2 to 4-4
block diagram, 4-3
timing I/O circuitry, 4-11 to 4-14
block diagram, 4-12
counter block diagram, 4-14
single-channel interval timing
(figure), 4-14
two-channel interval-scanning timing
(figure), 4-13
time-lapse measurement, 3-25 to 3-26
Timer Interrupt Clear Register, D-28
timing connections, 3-21 to 3-28
data acquisition timing
connections, 3-21 to 3-24
EXTCONV* signal timing (figure), 3-21
EXTUPDATE* signal timing
generating interrupts (figure), 3-24
updating DAC output (figure), 3-24
posttrigger timing (figure), 3-22
pretrigger timing (figure), 3-23