National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
Page 204
Index
Lab-PC+ User Manual
Index-8
© National Instruments Corporation
EXTUPDATE* signal
analog output circuitry
programming, E-20 to E-21
data acquisition timing, 3-23 to 3-24
generating interrupts (figure), 3-24
updating DAC output (figure), 3-24
description (table), 3-3
interrupt programming for analog output
circuitry, E-22 to E-23
F
fax technical support, F-1
FIFOINTEN bit
A/D interrupt programming, E-19
description, D-11
floating signal sources
definition, 3-5 to 3-6
signal connection considerations
differential connections, 3-8 to 3-9
recommended configurations (table), 3-6
single-ended connections, 3-10 to 3-11
freerun acquisition mode, multiple A/D
conversions
overview, E-5
programming steps, E-8 to E-10
frequency measurement, 3-26
application (figure), 3-26
fuse (parts locator diagram), 2-2
G
gain amplifier, programmable, 4-5
GAIN<2..0> bit, D-5
GATA0 bit
description, D-7
posttrigger mode
controlled acquisition mode, E-12
freerun acquisition mode, E-16
GATB0 signal (table), 3-3
GATB1 signal (table), 3-3
GATB2 signal (table), 3-3
GATE, CLK, and OUT signals
counter block diagram, 4-14
event-counting application (figure), 3-25
frequency measurement application
(figure), 3-26
general-purpose timing, 3-24 to 3-27
timing requirements (figure), 3-27
general-purpose timing connections
event counting, 3-25
application with external switch gating
(figure), 3-25
frequency measurement, 3-26
application (figure), 3-26
pretrigger timing (figure), 3-23
pulse and square wave generation, 3-25
pulse-width measurement, 3-25
specifications and ratings, 3-27
time-lapse measurement, 3-25 to 3-26
timing requirements for GATE and CLK
signals (figure), 3-27
ground-referenced signal sources
definition, 3-6
signal connection considerations
differential connections, 3-7 to 3-8
recommended configurations (table), 3-6
single-ended connections, 3-11 to 3-12
H
hardware installation, 2-15
HWTRIG bit
controlled acquisition mode
posttrigger mode, E-13
pretrigger mode, E-14
data acquisition timing, 3-21
description, D-10
multiple A/D conversions using EXTTRIG
signal, E-11
I
IBF signal
description, 3-16
Mode 1 input timing, 3-18
Mode 2 bidirectional timing, 3-20
Port C signal assignments (table), 3-16
IBFA status word, Port C
Mode 1 input, E-28
Mode 2 operation, E-32
IBFB status word, Port C, E-28
initializing Lab-PC+, E-1 to E-2
input configurations, 3-7 to 3-27