National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - Manual (Page 175)

Appendix E Register-Level Programming
© National Instruments Corporation E-19 Lab-PC+ User Manual
another N samples and the cycle repeats. The operation stops when the sample counter (Counter
A1) decrements to 0. Use the following sequence to configure the Lab-PC+ for single-channel
interval acquisition mode.
1. Write the count to the Interval Counter Data Register and strobe it in the counter.
2. Write the channel number and gain in Command Register 1. Write 0 to the SCANEN bit.
3. Write 1 to the INTSCAN bit in Command Register 4. Configure the EOIRCV bit with the
desired value.
4. Configure the remainder of the data acquisition circuitry as specified in any of the previous
outlines.
5. After programming the sample-interval counter (Counter A0) and the sample counter
(Counter A1), or configuring the circuitry to use EXTCONV*, configure the interval-
scanning counter (Counter B1) if necessary. Use the following sequence to program the
interval-scanning counter. All writes are 8-bit write operations. All values are hexadecimal.
a. Write 74 to the Counter B Mode Register (select Mode 2).
b. Write the least significant byte of the interval count to the Counter B1 Data Register.
c. Write the most significant byte of the scan-interval count to the Counter B1 Data
Register.
6. Use a software trigger to initiate the operation.
Note that you must program the sample counter (Counter A1) for the total number of samples
desired. For example, if you want to acquire 2,000 samples in batches of 100, load the Interval
Counter with 100 and load the sample counter with 2,000.
A/D Interrupt Programming
Two different interrupts are generated by the A/D circuitry:
• An interrupt whenever a conversion is available to be read for FIFO
• An interrupt whenever an error condition (overflow or overrun) is detected
These two interrupts are enabled individually.
To use the conversion interrupt, set the FIFOINTEN bit in Command Register 3. If this bit is set,
an interrupt is generated whenever the DAVAIL bit in the Status Register is set. This interrupt
condition is cleared when the FIFO is emptied by reading its contents.