Dmatc interrupt clear register – National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
Page 136
Register Map and Descriptions
Appendix D
Lab-PC+ User Manual
D-20
© National Instruments Corporation
DMATC Interrupt Clear Register
Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt request
asserted when a DMA terminal count pulse is detected.
Address:
Base address + 0A (hex)
Type:
Write-only
Word Size:
8-bit
Bit Map:
Not applicable, no bits used
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