Intel D865PCD - Manual (Page 24)

Intel Desktop Board D865PCD Technical Product Specification
24
Channel A DIMM Channel B DIMM
Dual Channel Configuration with Dynamic Mode
(DIMMs matched)
OM17045
Intel
82865P
MCH
Throughput
Level
Configuration
Characteristics
Highest Dual Channel with Dynamic Mode DIMMs matched
Single Channel with Dynamic Mode Single DIMM
Lowest
Single Channel without Dynamic Mode DIMMs not matched
Figure 6. Example of Single Channel Configuration without Dynamic Mode
1.6 Intel ® 865P Chipset
The Intel 865P chipset consists of the following devices:
• Intel 82865P Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• Intel 82801EB I/O Controller Hub (ICH5) with AHA bus
• Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH5 is a centralized controller for the board’s I/O
paths. The FWH provides the nonvolatile storage of the BIOS.
For information about Refer to
The Intel 865P chipset http://developer.intel.com/
Resources used by the chipset Chapter 2
1.6.1 Universal 0.8 V / 1.5 V AGP 3.0 Connector
The AGP connector supports the following:
• 4x, 8x AGP 3.0 add-in cards with 0.8 V I/O
• 1x, 4x AGP 2.0 add-in cards with 1.5 V I/O
• AGP Digital Display (ADD) cards