Intel OCPRF100 MP - Manual (Page 137)

OCPRF100 MP Server System Technical Product Specification
Revision 1.0
130
† Note that although the keypad press-release cycle may be as short as zero, worst case, the firmware is only
required to detect a cycle as short as 50 ms.
10.2.11.2 NMI Switch
The NMI push button is hidden behind the main front panel bezel, except for a small “pinhole”
access hole. This is done to prevent inadvertent activation of the NMI switch. The NMI switch is
routed directly to the BMC. There is no interface to the FPC.
10.2.12 I
2
C Interfaces
The FPC interfaces to two I
2
C buses; the FPC’s I
2
C bus and the global I
2
C bus. These are
described in the following subsections.
10.2.12.1 The FPC Private I
2
C Bus
The FPC’s private I
2
C bus is used for the FPC to communicate with dumb I
2
C devices that do not
support multimaster mode. These are shown in Figure 10-2: Devices Not Supporting Multimaster
Mode.
Potential Switch Cycle characteristics (Press to Release)
[no firmware requirements derived from this row] 0 200 Infinity
Table 10-8: Debounce Characteristics and Requirements