Intel OCPRF100 MP - Manual (Page 131)

OCPRF100 MP Server System Technical Product Specification
Revision 1.0
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All four latches may be read by the microcontroller. Reading by the microcontroller causes the
latch to be deasserted (assuming that the asserting signal is also deasserted).
With this interrupting scheme, it is suggested that the FPC use the power interrupt in level mode,
not edge mode. This is because a reassertion of an interrupting source at the wrong time could
prevent the interrupt pin from being toggled.
10.2.6.3 Front Panel Power Switch
The paramount design concern is the capture of an asserted switch with a microcontroller/firm-
ware design that experiences starved threads, specifically the thread that polls the power switch.
(In normal real time control, a starved thread is an indication of abnormal operation that would
cause a fatal error and abortion of microcontroller operation.) This is addressed by latching the
asserted state in hardware via the PWR_SWT_LATCH. This latch is set whenever the switch is
asserted. Whenever the switch is read, the latch is cleared. Therefore, when the starved thread
regains the FPC, it can read the latch. If the switch was asserted after the last polling, the latch
reads a one.
10.2.6.4 Hardware Control of Power Supply ON Command
The following describes the hardware control over the PS_PWR_ON (output) signal. The FPC
has only marginal control over this signal. The system-power-on command (PS_PWR_ON) is
asserted by the FPC via the PS_PWR_ON (output) signal, as long as there is not a 240 volt-
amp incident.
10.2.6.5 Default Power State
The default power state is OFF. This is the state that the front panel commands for the main
power via the PS_PWR_ON (output) signal. During normal operation the firmware must assert
the PS_PWR_ON (output) signal to turn on the supplies. This is controlled from the PLD. During
a firmware-driven PLD download, the PLD’s outputs become tristated. When tristated, the power
supplies are commanded on via an external pull-up resistor.
10.2.6.6 Dual Speed Fan Power
The system cooling fans typically operate at low voltage to minimize acoustic noise. Under nor-
mal conditions, the fans run at this slower, quieter speed. When a fan failure is sensed, the fan
speed is set to high. Also, if the ambient temperature sensor reads 31 degrees or higher, the fan
speed will be set to high (there are 2 degrees of hysteresis built into this algorithm, so the ambi-
ent temperature must drop to 29 degrees before the fan speed is reduced to low again). The
high/low decision is made by the FPC, via the FULL_FAN_SEL_L signal.
The fan voltage is derived via a buck converter from 12 V, and is current limited at 9 A. Maximum
current during high speed operation is 5.04 A.
10.2.7 Reset