Intel 8XC196Lx - Manual (Page 42)

8XC196L X SUPPLEMENT
4-8
PTSSRV Address:
Reset State:
0006H
0000H
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has
been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding
PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS
interrupt is called, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine must set
the PTSSEL bit to re-enable the PTS channel.
15 8
LA — EXTINT — RI TI SSIO1 SSIO0 —
7 0
— — AD EPA0 EPA1 EPA2 EPA3 EPA x
15 8
LB — EXTINT — RI TI SSIO1 SSIO0 J1850ST
7 0
J1850RX J1850TX AD EPA0 EPA1 EPA2 EPA3 EPA x
15 8
LD — EXTINT — RI TI SSIO1 SSIO0 —
7 0
— — — EPA0 EPA1 EPA2 EPA3 EPA x
Bits Function
14:0 † A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt
through its standard interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt Standard Vector
EXTINT EXTINT pin 203CH
Reserved † — 203AH
RI SIO Receive 2038H
TI SIO Transmit 2036H
SSIO1 SSIO 1 Transfer 2034H
SSIO0 SSIO 0 Transfer 2032H
J1850ST (LB) J1850 Status 2030H
J1850RX (LB) J1850 Receive 202EH
J1850TX (LB) J1850 Transmit 202CH
AD (LA, LB) A/D Conversion Complete 202AH
EPA0 EPA Capture/Compare Channel 0 2028H
EPA1 EPA Capture/Compare Channel 1 2026H
EPA2 EPA Capture/Compare Channel 2 2024H
EPA3 EPA Capture/Compare Channel 3 2022H
EPA x †† Multiplexed EPA 2020H
†† PTS service is not useful for shared interrupts because the PTS cannot readily
determine the source of these interrupts.
† Bit 13 is reserved on the 8XC196L x devices and bits 6–8 are reserved on the 87C196LA and
83C196LD. For compatibility with future devices, write zeros to these bits.
Figure 4-6. PTS Service (PTSSRV) Register