Sundance SMT321 - Manual (Page 6)

Table of Figures
Figure 1.Functional Block Diagram of the SMT321. ........................................................ 8
Figure 2. Data path of the FPGA and module................................................................ 10
Figure 3. SMT321 Power Structure. .............................................................................. 13
Figure 4. Reset Generation and Distribution. ................................................................ 14
Figure 5. Trigger path from FPGA to output. ................................................................. 15
Figure 6. Analog signal path from FPGA to output. ....................................................... 16
Figure 7. Clock path from FPGA to output..................................................................... 16
Figure 8. Connectors present on the SMT321............................................................... 17
Figure 9. Split JTAG Cable for SMT321. ....................................................................... 17
Figure 10. Digital IOS connector present on the SMT321.............................................. 18
Figure 11. Setup Packet Structure. ............................................................................... 22
Figure 12. Control Register Read Sequence. ................................................................ 23
Figure 13. Clock output equation................................................................................... 25
Figure 14. Trigger with 1 clock high and 1 clock low...................................................... 25
Figure 15. One pulse generated on trigger A output (ChannelATrigPulse).................... 26
Figure 16. Module Top View. ........................................................................................ 28
Figure 17. Module Bottom View. ................................................................................... 28
Figure 18. Trigger A: 0 high time 0 low time. Positive side of signal. ............................. 29
Figure 19. Trigger B: 10 high time 2 low time. Positive side of signal. ........................... 30
Figure 20. Clock B: Freq 62MHz in time. Positive side of signal.................................... 31
Figure 21. Clock B: Freq 62MHz in frequency. .............................................................. 32
Figure 22. Clock B: 233MHz in time. Positive side of signal. ......................................... 33
Figure 23. Clock B: 233MHz in frequency. .................................................................... 34
Figure 24. VCO2: 247MHz in time................................................................................. 35
Figure 25. VCO2: 247MHz in frequency........................................................................ 36
Figure 26. VCO1: 91MHz in time................................................................................... 37
Figure 27. VCO1: 91MHz in frequency.......................................................................... 38