Sundance SMT321 - Manual (Page 11)

The enable signals are split up into one for both continuous triggers and one each for the
pulse triggers. Separate enables are needed on the pulse generators because when
asserted a single pulse goes out on the channel and then the channel stays inactive till
the next enable on the pulse generator.
There are six 16-bit registers for the trigger operation block in firmware. They are split up
between the two channels thus three per channel. Each channel has a trigger high
register, trigger low register and a pulse high register. The first two registers are used in
the generation of the continuous trigger. The first register sets up the high time for the
trigger and the second the low time for the trigger. The last register sets up the high time
for the single pulse. The channel is switched between the two signals using a multiplexer
and the multiplexer signal for the certain channel.
Digital Pod Registers and Digital Pod Setup
As the comport is implemented on the SMT321 to be able to only send data in 16 bits
the digital pod’s registers are split up into two as it requires a 24bit data stream for setup.
The comport sends the first data, which consists of the upper (MSB) 16 bits of the data
word, to the digital pod and then a second transmit which contains the lower (LSB) 8 bits
of the digital pod’s data word. Thus 16 bits + 8 bits = 24 bits.
These two registers are then combined in a single register which is sent to the digital
pod setup by sending the update signal to the digital pod firmware module. Here the
firmware generates a sequence of handshaking protocols and clocks the 24bit word into
the digital pod. The pod has a resolution of 1024 positions which is dealt into a 0 Volt to
18 Volt swing on the VCO’s. This results into a 0.0175V step size. But most of the VCO’s
only operate from 1 Volt to 16 Volts thus some resolution is lost to these operating
regions.
Clock Registers and Clock Setup
There are two 16 bit registers in the clock setup. The data word needed for the setup of
the clock is only 14 bits long thus the 16 bit registers are sufficient to receive data from
the comport in one cycle. Each clock synthesizer (two present on the board) has its own
register. When the comport receives the data for the clock registers it configures the
registers accordingly and asserts the enable pin on the clock setup firmware.
The clock setup firmware generates the handshaking protocols and then clocks the data
into the synthesizers. The synthesizers then generate a clock depending on the setup
given by the user.
2.4 Clock Structure
An external 100MHz oscillator provides the FPGA with a clock. All the internal firmware
operates on this frequency.
The Microcontroller is driven by an external 8MHz resonator.