Sundance SMT321 - Manual (Page 21)

137 Adjust VCO Config 0 LVTTL
140 Dig IOS Fpga Bus 0 LVTTL
141 Dig IOS Fpga Bus 1 LVTTL
Table 4. User IOS of FPGA in SMT321.
3 Description of interfaces
3.1 MSP430 Interface
A custom interface is implemented between the FPGA and the microprocessor. The
microprocessor is the master and the FPGA is the slave. This interface is used for
issuing a reset command to the FPGA, and for the microprocessor to write the ADC
temperature and silicon serial number to the FPGA.
3.2 Digital Pod Interface
A three wire uni-directional control interface is implemented between the FPGA and the
digital trim-pod. This pod sets the voltage for the VCO’s that generates the analog signal
outputs.
3.3 Clock Synthesizers Interface
A three wire uni-directional control interface is implemented between the FPGA and the
clock synthesizers. These synthesizers control the clock output of the SMT321.
3.4 TIM Interface
The SMT321 implements Comports 0 and 3. All configuration data is received and
transmitted over these two ports. Comport 3 is implemented as a uni-directional receive
interface and only receives data sent to the SMT321. Comport 0 is implemented as a
uni-directional transit interface and only transmits data from the SMT321.
The Global Bus Interface is not implemented on the SMT321. Refer to [1] for a more
detailed description of the TIM interface.
4 Control Register Settings
The Control Registers in the SMT321 control the complete functionality of the SMT321.
These Control Registers are setup via the Comports. The settings of the triggers, the
clock settings and the settings of the analog signals settings can be configured via the
Control Registers.
4.1 Control Packet Structure
The data passed on to the SMT321 over the Comports must conform to a certain packet
structure. Only valid packets will be accepted and only after acceptance of a packet will