Sundance SMT321 - Manual (Page 4)

Table of Contents
1 Introduction .................................................................................................................. 7
1.1 Overview ............................................................................................................... 7
1.2 Module Features.................................................................................................... 7
1.3 Related Documents ............................................................................................... 7
2 Functional Description.................................................................................................. 8
2.1 Module Overview ................................................................................................... 8
2.2 Main Analog Characteristics .................................................................................. 9
2.3 Data Stream Description...................................................................................... 10
2.3.1 Description of Internal FPGA Blocks ............................................................. 10
2.4 Clock Structure.................................................................................................... 11
2.5 Power Supply and Reset Structure ...................................................................... 12
2.6 MSP Functionality................................................................................................ 14
2.7 Trigger Output ..................................................................................................... 14
2.8 Analog Signal Output........................................................................................... 15
2.9 Clock Output........................................................................................................ 16
2.10 Connectors Pin outs .......................................................................................... 16
2.10.1 FPGA & MSP JTAG connector.................................................................... 17
2.10.2 Digital IOS................................................................................................... 18
2.10.3 Trigger Connectors ..................................................................................... 18
2.10.4 Analog Signal Connectors ........................................................................... 18
2.10.5 Clock Connectors........................................................................................ 18
2.11 FPGA IOS ......................................................................................................... 18
3 Description of interfaces............................................................................................. 21
3.1 MSP430 Interface................................................................................................ 21
3.2 Digital Pod Interface ............................................................................................ 21
3.3 Clock Synthesizers Interface ............................................................................... 21
3.4 TIM Interface ....................................................................................................... 21
4 Control Register Settings ........................................................................................... 21
4.1 Control Packet Structure...................................................................................... 21
4.2 Reading and Writing Registers ............................................................................ 22
4.3 Memory Map ....................................................................................................... 23
4.4 Register Descriptions........................................................................................... 24
4.4.1 Com In Scratch Registers ............................................................................. 24
4.4.2 Clock Control Registers................................................................................. 24
4.4.3 Trigger Control Registers .............................................................................. 25
4.4.4 Digital Pod Registers..................................................................................... 26
4.4.5 Digital IOS output register ............................................................................. 26
4.4.6 Firm Ware Version ........................................................................................ 27
4.4.7 Com Out Scratch Registers ........................................................................... 27