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Version 1.2.0
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SMT398 User Manual
Table of Figures
Figure 1:SMT398 Block Diagram .............................................................................................9
Figure 2: FPGA configuration in SelectMap mode using CPLD.............................................14
Figure 3: Comport word Byte order ........................................................................................15
Figure 4: CPLD state machine ...............................................................................................16
Figure 5: V II Configuration Bitstream Word Format ..............................................................20
Figure 6: JTAG Chain on the SMT398 ...................................................................................23
Figure 7:SMT398 ZBT Memory Banks arrangement .............................................................26
Figure 8: ZBT Constraints file signal names ..........................................................................27
Figure 9:SMT398 QDR Width expansion arrangement..........................................................28
Figure 10: QDR Constraints file signal names .......................................................................29
Figure 11:SMT398 Comports connections.............................................................................30
Figure 12: Comport Constraints file signal name ...................................................................31
Figure 13: SHB Connector .....................................................................................................32
Figure 14: SHB constraints file control signals names. ..........................................................35
Figure 15: SHB constraints file data signals names...............................................................35
Figure 16: SHB constraints file User pins signals names.......................................................36
Figure 17: Global Bus constraints file signal names. .............................................................37
Figure 18: DC/DC converter dimensions (in inches) ..............................................................39
Figure 19:SMT398 Components placement-Top view ...........................................................46
Figure 20: SMT398 Components placement-Bottom view.....................................................47
Figure 21: Top View QSH 30 .................................................................................................48
Figure 22: Top View of JTAG/Multilinx headers .....................................................................50
Table of Tables
Table 1: FPGA Choices..........................................................................................................21
Table 2: ZBTRAM sizes .........................................................................................................26
Table 3: QDR RAM sizes .......................................................................................................28
Table 4: External clock specification ......................................................................................38
Table 5: powering the devices................................................................................................39
Table 6: Duplicate pins...........................................................................................................42
Table 7: Virtex II, ZBT/QDR combinations in FULL configuration ..........................................44
Table 8: Virtex II, ZBT combinations in BASIC configuration .................................................45
Table 9: SHB interfaces table.................................................................................................49
Table 10: Connector J13-JTAG Header.................................................................................50
