Sundance SMT398 User Manual
Page 18
Version 1.2.0
Page 18 of 52
SMT398 User Manual
After a Global Reset pulse, a DSP module drives CONFIG low and keeps it low by
default.
After Reset and loading of the DSP application, CONFIG can be driven the following
way:
#include “SMT3xx.h”
#define CONFIG_BIT 1<<6
int main()
{
*CONFIG |= CONFIG_BIT; //tristates CONFIG (Pull-ups on the carrier board pull CONFIG high)
*CONFIG &= (UINT32)~CONFIG_BIT;//CONFIG is driven low
//delay while the FPGA is configured
*CONFIG |= CONFIG_BIT;
}
This feature can be interesting in systems where:
• The FPGA needs to implement multiple functions spread in different
bitstreams that are needed at different stages of the application.
• The system needs to keep running and can’t be interrupted by a global Reset
pulse when the SMT398 FPGA needs to be configured with a new bitstream.
• The FPGA needs to be kept in reset BUT NOT reprogrammed.
o
Config low Pulse: the CPLD drives the FPGAReset_In signal low and
keeps it low.
o
ENDKEY: The CPLD drives the FPGAReset_In signal high.