Sundance SMT398 - Manual (Page 15)

Version 1.2.0 Page 15 of 52 SMT398 User Manual
Decode Commands
At power up, after a TIM global Reset, or once the FPGA configuration process is
over, the CPLD reads any word coming on its Comport.
If a received word cannot be recognized as a command, the word is read completely
but ignored. The CPLD recognizes the following two commands:
• STARTKEY
(0xBCBCBCBC)
• ENDKEY
(0xBCBCBC00)
Comport Receiver
At power up or after a TIM global Reset, the CPLD takes control of Comport 3.
Once the ENDKEY command is received, the CPLD releases Comport 3.
The Comport communication is performed in 32-bit words, where each word consists
of four consecutive bytes. The Comport protocol transmits words starting with the
least-significant byte (LSByte), i.e. byte0, as shown in
Figure 3: Comport word Byte
order , and 1 byte at a time.
Byte3 Byte2 Byte1 Byte0
31 24 23 16 15 8 7 0
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3: Comport word Byte order
Configure FPGA
The signals INITn and DONE are CPLD inputs, the other one are CPLD outputs that
the CPLD drives to configure the FPGA.
On reception of the STARTKEY command the CPLD clears the FPGA configuration
memory by asserting the PROGRAMn pin low. On INITn going low, the CPLD brings
PROGRAMn high and waits for INITn to come back high before starting the FPGA
configuration.
Afterwards, the CPLD asserts CSn and WRITEn low for the rest of the configuration
process.
The CPLD pulses high CCLK to loads in the FPGA any new byte present on the
Comport by.