Sundance SMT398 - Manual (Page 13)

Version 1.2.0 Page 13 of 52 SMT398 User Manual
FPGA Configuration
The FPGA can be configured 2 different ways:
• Using Comport 3 to provide the bitstream. (See
The service CPLD )
• Using the on-board JTAG header and Xilinx JTAG programming tools. (See
FPGA in system programming )
Electrical Interface
The service CPLD
The CPLD allows for FPGA configuration in slave SelectMap mode.
At power up the FPGA is not configured.
LED L5 (See Figure 19:SMT398 Components placement-Top view , bottom right
hand corner of the picture) will be lit upon FPGA configuration.
At power up or after a Reset of the SMT398, the CPLD is configured and
implements a Comport link receiver on Comport 3.
The CPLD is connected to Comport number 3 of the SMT398 TIM connector.
Consequently, the Comport on the other end of the link must be configured as
transmitter at power-up or after reset, i.e. Comport channels 0, 1, or 2.
The typical SMT398 user does not need an in depth understanding of the
configuration sequence and of the Virtex II. However, for the purpose of debugging
and designing for the SMT398 an overview of the necessary configuration protocol
and bitstream formatting is recommended.
Therefore, this section describes the CPLD functions, the Virtex II bitstream format
and the necessary bitstream re-formatting when downloading the bitstream to the
FPGA via CPLD + Comport 3.
Figure 2: FPGA configuration in SelectMap mode using CPLD provides waveforms to
illustrate the descriptions below.