Sundance SMT398 - Manual (Page 16)

Version 1.2.0 Page 16 of 52 SMT398 User Manual
The CPLD does not implement any operation on the bitstream and passes it straight
through to the FPGA once the STARTKEY has been decoded and until the ENDKEY
is decoded.
Once the FPGA DONE pin has gone high, LED L5 (See Figure 19:SMT398
Components placement-Top view , bottom right hand corner of the picture) becomes
on, indicating that the FPGA configured.
The CPLD disables the SelectMap interface and waits for the ENDKEY command on
Comport3.
Once the ENDKEY command is received, the CPLD releases Comport 3.
Reset Control
INIT
CONFIG
IDLE
TIM Reset or TIM Config
FPGA Configured and
ENDKEY Received
FPGA Configured
and ENDKEY Received
STARTKEY Received
Figure 4: CPLD state machine