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Figure 20: smt398 components placement-bottom view, Figure 20: smt398, Components placement-bottom view – Sundance SMT398 User Manual

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Version 1.2.0

Page 47 of 52

SMT398 User Manual

Figure 20: SMT398 Components placement-Bottom view

U1 : Xilinx FPGA

U2: Xilinx CPLD

U3: ZBTRAM Bank1

U4: ZBTRAM Bank2

U5: ZBTRAM Bank3

U6: ZBTRAM Bank4

U10: QDR Bank1

U11: QDR Bank2

XTAL1: Onboard oscillator

J6: (Top view, bottom left corner), External clock input connector

These 2 Banks share the same address lines (See

Figure 9:SMT398 QDR Width expansion arrangement.)