Sundance SMT398 - Manual (Page 19)

Version 1.2.0 Page 19 of 52 SMT398 User Manual
Notes:
• TIM CONFIG is only available on SMT398 v3. The SMT398 version is written
on TOP of the board (See Figure 19:SMT398 Components placement-Top
view ).
• TIM CONFIG needs CPLD code version 2.1 or above (Written on a sticker on
the CPLD. (See Figure 19:SMT398 Components placement-Top view ).
• The Comport3 is reserved for the CPLD and cannot be made available to the
FPGA.
• CONFIG needs switch SW1 position 8 to be ON. (See
Figure 20: SMT398
Components placement-Bottom view )
• If you have more than one DSP module on a carrier and that you want to use
the CONFIG line, you must decide which TIM is going to be the master and
have the other DSP modules to tri-state their CONFIG line at the start of their
application by writing ‘1’ to the corresponding register bit. (See the
SMT6400
help file for information on the DSP TIM CONFIG signal).
Summary:
The Reset level on the SMT398 FPGA is active low.
The reset line to be used is FPGAReset_in on pad AM20 for FPGAs in the big
package (FF1152) and AK18 for the smaller package FPGAs.
Virtex II Bitstream Format
The Virtex II SelectMap interface is an 8-bit interface on the device with data pins
labeled D[7:0]. The configuration bitstreams can be written eight bits per clock cycle.
The Virtex II configuration bitstreams generated by BitGen (.bit files) contain a mix of
commands and data on 32 bit word boundaries, shown in
Xilinx application note 138
page 20. This format assumes D0 is considered the MSBit as shown Figure 5: V II
Configuration Bitstream Word Format .