Sundance SMT398 - Manual (Page 17)

Version 1.2.0 Page 17 of 52 SMT398 User Manual
TIM Global Reset
The CPLD is connected to a TIM global Reset signal provided to the SMT398 via its
TIM connector J4 pin 30. (See
Figure 19:SMT398 Components placement-Top view ).
The TIM global Reset signal is also available for the FPGA but the CPLD provides
another signal called
FPGAReset_In that offers a better Reset control over the
FPGA.
At power up or on reception of a
low TIM global Reset pulse , the CPLD drives the
FPGAReset_In signal low and keeps it low .
When the ENDKEY has been received , the CPLD drives FPGAReset_in high .
I recommend that you use FPGAReset_In for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also
avoid possible conflicts on Comport 3 if your FPGA design implements it.
The Reset control is operated by the CPLD line FPGAReset_In.
DO NOT use TIM GLOBAL Reset unless you have a very specific need for your
application.
TIM CONFIG
A TIM CONFIG signal coming from the TIM connector J4 pin 74. (See Figure
19:SMT398 Components placement-Top view and Figure 11:SMT398 Comports
connections ) is available to the CPLD.
CONFIG falling has the same effect on the SMT398 CPLD as a TIM global Reset
pulse.
On detection of a falling edge on the CONFIG line, the CPLD drives the
FPGAReset_In signal low and keeps it low.
CONFIG provides a means of reprogramming the FPGA without having to drive the
TIM Global Reset signal.
Therefore any other modules sensitive to the TIM global Reset signal will not be
affected and can keep running their application.
CONFIG is driven from another TIM site on the carrier board, for instance, from a
DSP module running an application. (See
the SMT6400 help file for information on
the DSP TIM CONFIG signal).
Writing ‘1’ to the DSP CONFIG bit in the config register tristates the line (pull-ups on
the carrier board pull CONFIG high)
Writing ‘0’ to the DSP CONFIG bit in the config register makes the CONFIG signal go
low.