Table 1: fpga choices – Sundance SMT398 User Manual
Page 21
Version 1.2.0
Page 21 of 52
SMT398 User Manual
This Xilinx Virtex II, is responsible for the provision of up to 4 SHBs, up to 6
Comports, the global bus and QDR/ZBT memory banks (In FULL configuration, see 0
Ordering information:)
CLB(1 CLB = 4 slices = Max 128
bits)
SelectRAM Blocks
Device
Syste
m
gates
Array
Row x
Col
Slices
Maximum
distribute
d RAM
Kbits
Multiplie
r
blocks
18-Kbit
Block
Max RAM
(Kbits)
DCM
s
XC2V1000
1M
40x32
5,120
160
40
40
720
8
XC2V1500
1.5M
48x40
7,680
240
48
48
864
8
XC2V2000
2M
56x48
10,752
336
56
56
1,008
8
XC2V3000
3M
64x56
14,336
448
96
96
1,728
12
XC2V4000
4M
80x72
23,040
720
120
120
2,160
12
XC2V6000
6M
96x88
33,792
1,056
144
144
2,592
12
XC2V8000
8M
112x104
46,592
1,456
168
168
3,024
12
Table 1: FPGA Choices
The Xilinx FPGA is configured from one of several modes:
Slave SelectMAP.
JTAG/Boundary scan
And from one of several sources:
Comport 3 (Using Slave SelectMAP)
Parallel cable III-IV (Using JTAG)
MultiLINX cable. (Using JTAG or Slave SelectMAP)
At power up the FPGA is not configured.
LED L5 (See
Figure 19:SMT398 Components placement-Top view
hand corner of the picture) will be lit upon FPGA configuration.