Sundance SMT398 - Manual (Page 41)

Version 1.2.0 Page 41 of 52 SMT398 User Manual
Verification Procedures
The specification (design requirements) will be tested using the following:
1) Power module test.
2) FPGA configuration using CPLD and/or JTAG connector.
3) Comport transfers between a SMT376 and the SMT398.
4) ZBT and QDR memory tests.
5) SHB connector Pins Test using SHB tester PCBs.
6) Global Bus transfers between SMT398 and SMT310Q onboard SRAM.(Not
yet implemented)
7) External clock I/O tested with scope.
Review Procedures
Reviews will be carried out as indicated in design quality document QCF14 and in
accordance with Sundance’s ISO9000 procedures.
Validation Procedures
The validation procedure is happening during the verification procedure.
Test that all the memories are accessible by the FPGA as well as all the
communication links.
FPGA Constraint File general Information
Because the Virtex FF896 and FF1152 packages are footprint and pinout compatible,
the SMT398 offers a high level of flexibility in the choice of the FPGA fitted.
SMT398_896_in_1152_.xls is a spreadsheet showing ALL signal connections for
ALL FPGAs that can be fitted on the SMT398.
You can see at a glance which signals are available or not for ALL FPGAs.
It also allows to sort pins automatically by names beginning with, or containing a
string etc…using the drop down menus.
This file also shows a particular feature of the SMT398: some signals can be
accessed from 2 different pin locations on the FPGA to allow an easier routing of
your design. (The duplicate pin is indicated by “name_2”).
See Table 6: Duplicate
pins
For example, on a XC2V6000, you could use AL33 or W25 to access Z3CS1N.