Sundance SMT391-VP - Manual (Page 39)

Version 1.3 Page 39 of 41 SMT391-VP User Manual
The state machine waits for the AdcFlag to go high before it switches to the Initialize
state. In this state the InternalDataRegister is built up using the data and address
input registers and then clocked out during the following two states - ClockLow and
ClockHigh. After the counter is finished counting all the bits clocked out in these two
states it jumps to LastClockLow which sends the first of the termination sequence
and then jumps to the state Load which finalizes the configuration by pulling AdcSLd
high.